The present invention relates to interferometric devices and methods for optically analyzing surfaces, for example, such as the surfaces of semiconductor wafers, semiconductor devices, magnetic surfaces, and the like.
Interferometers are commonly used for testing the shape and topography of surfaces. Good interferometers have height sensitivity in the sub-nanometer range, providing two-dimensional maps in rapid, non-contact operation. A large variety of optical interferometer configurations exist, as well as processing techniques to derive surface topography maps from the measured interferogram intensities.
The fringes of the interferogram are governed by the phase difference between a test beam and a reference beam. The phase of the test beam includes a propagation phase delay and a phase shift on reflection at the surface of a test object or test piece. While the propagation phase is indicative of the test surface height, the phase shift on reflection is affected by the material properties, composition, and surface features of the test piece. Although the variation of the phase shift on reflection is usually considered to be a source of error in the surface topography measurement, additional information about these test object properties carried in the interferograms can be extracted and exploited.
For test surfaces with uniform properties, the phase shift on reflection is constant across the interferogram and only contributes to a constant height offset, like the position alignment of the test piece. It does not affect the surface topography measurement. Examples include a dielectric glass surface, where the phase shift on reflection is pi (π) radians, or an aluminized mirror surface, where the phase shift is different from π but uniform in the interferogram.
For non-uniform test surfaces, the phase shift on reflection varies across the interferogram and hence affects the topography measurements. Examples include read-write head surfaces in magnetic hard disks, where part of the test surface is a dielectric and another part is metallic, or a patterned semiconductor wafer surface in the copper chemical-mechanical-polishing (“CMP”) process, where part of the test surface consists of metallic copper and other parts consist of dielectric multilayer film stacks on a silicon wafer.
In integrated circuit manufacturing, the semiconductor switches in the wafer material need to be connected by conductive wiring to obtain functioning circuits. This wiring structure is manufactured in layers by depositing a metal overcoat on the insulating layers that are patterned with vias and trenches, and then removing all excess metal material by CMP. Each metal wiring layer can contain several dielectric insulating layers of different materials such that, in general, the top surface includes metal areas and areas with complex multilayer film stacks.
After the CMP process, only the vias and trenches are filled with metal, thus functioning as conductive paths. Currently, tungsten is commonly used for the first metal layer over the silicon, while higher metal layers mainly use copper. The CMP process exhibits material- and geometry-dependent removal rates, leading to difficulties in obtaining an ideally flat top surface for metal and insulator. One main characteristic of the top surface topography is called “dishing,” which refers to the surface height difference by which the metal surface is lower than the surrounding insulator. Another characteristic is called “erosion,” which refers to the surface height difference by which insulator material interspersed with metal is lower than solid insulator. Another item of interest in the manufacturing process is the film thickness of the dielectric layers as well as of the metal lines. Furthermore, the width, shape, sidewall angle, or in general the micro-structure, of the fine metal lines frequently are of interest.
Currently, the top surface topography of CMP products is measured with tactile stylus tools or atomic-force profilers. The contacting nature of these profilers restricts their usage to special targets in the scribe line between chips. Furthermore, the measurement process is slow because it is inherently a single-point measurement where profiles or two-dimensional maps have to be built up sequentially. The film thickness is measured using spectrophotometers or ellipsometers, which are unable to provide information about the surface topography. The width and shape of fine metal lines, or in general of micro-structures, are measured by atomic-force profilers or scatterometers.
U.S. Pat. No. 6,545,763 to Kim et al. discloses a method for the measurement of surfaces with thin films based on white-light scanning interferometry which extracts a spectral phase distribution from the temporal intensity or time-domain signal by Fourier transform. The spectral phase distribution is then compared with a theoretically generated phase distribution by modeling the measured surface with different properties, such as film thicknesses, refractive indexes, etc. Once the best match is found, the surface properties as well as the surface topography are determined. Difficulties can arise with thinner films using this approach.
The available technology has been limited and in some senses deficient, for example, in that known apparatus and methods are unable to provide fast, non-contact surface topography measurements in the presence of varying phase shifts on reflection. The need also remains for apparatus and methods that can quickly and efficiently measure surface topography as well as surface composition. The term “surface composition” as used herein, broadly construed, means not only the chemical or material composition at the surface or top plane of the object, but other properties and characteristics at or below the surface. It can include, for example, film layers lying at or beneath the surface or top plane of the material, optical properties such as refractive index, surface microstructure, electrical properties such as conductivity or resistivity, and the like.